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DS587 Datasheet, PDF (11/20 Pages) Xilinx, Inc – Selectable ADC resolution
XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Table 7: Device Global Interrupt Enable Register (GIE) Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
Master Enable for routing Device Interrupt to the
System Interrupt Controller.
0
Global Interrupt Enable Read/Write ’0’ ’1’ = Enabled
’0’ = Disabled
1 to 31
Unused
N/A
0 Unused
IP Interrupt Status and Interrupt Enable Registers
The XPS ADC supports a single interrupt condition, FIFO Non-empty, which indicates that conversion
samples are available. The interrupt status and interrupt enable bits are located at bit-position 31 in the
IP Interrupt Status Register (IPISR) and IP Interrupt Enable Register (IPIER), respectively. See Figure 5,
Table 8 and Table 9.
X-Ref Target - Figure 5
Unused
FIFO Non-empty
0
31
DS587_05_090809
Figure 5: Interrupt Status and Interrupt Enable Register
Table 8: Interrupt Status Register (IPISR) Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
0 to 30
Unused
N/A
0 Unused
FIFO Non-empty Interrupt.
31
FIFO Non-empty
Read/TOW
’0’
’1’ = ADCout Data FIFO contains the
converted data
’0’ = ADCout Data FIFO is empty
Table 9: Interrupt Enable Register (IPIER) Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
0 to 30
Unused
N/A
0 Unused
Enable/Disable the FIFO Non-empty
Interrupt.
31
FIFO Non-empty
Read/Write ’0’ ’1’ = Enabled
’0’ = Disabled (masked)
ADC Control Register (ADCCR)
The ADC Control Register contains the Enable Conversion bit (EC) and the Filter Settle Time Multiplier
(FSTM). The EC bit will enable/disable the Analog to Digital Conversion process. FSTM is a binary
value, which depends on the RC characteristics of the low pass filter being used for conversion of
DACout pulse train into equivalent analog signal. Bit sample time is effectively multiplied by Filter
Settle Time Multiplier (FSTM +1), so the user can configure the bit sample rate to match the Filter Settle
DS587 December 2, 2009
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Product Specification