DS587 Datasheet, PDF (7/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Table 3: XPS ADC I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
P37 Sl_MBusy[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave busy
P38 Sl_MWrErr[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave write error
P39 Sl_MRdErr[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave read error
Unused PLB Slave Interface Output Signals
P40 _{Sl_wrBTerm}
PLB
O
0
Slave terminate write burst
transfer
P41 Sl_rdWdAddr[0:3]
PLB
O
0
Slave read word address
P42 _{Sl_rdBTerm}
PLB
O
0
Slave terminate read burst
transfer
P43 Sl_MIRQ[0:
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Master interrupt request
XPS ADC Signals
P44 _DACout
ADC
O
0
Pulse string that drives the
external low pass filter.
P45
Sample
ADC
O
0
Sample and Hold. This signal is
true when ADC starts sampling
the input and can drive an
external Sample and Hold circuit.
P46
AgtR
ADC
I
-
Analog greater than Reference.
This is the output of external
comparator.
XPS ADC Design Parameters
To allow the user to create a XPS ADC that is uniquely tailored for the user’s system, certain features
are parameterizable in the XPS ADC design. This allows the user to have a design that utilizes only the
resources required by the system and runs at the best possible performance. The features that are
parameterizable in the XPS ADC core are as shown in Table 4.
DS587 December 2, 2009
www.xilinx.com
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Product Specification