DS587 Datasheet, PDF (6/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Table 3: XPS ADC I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
P8 PLB_BE[0: (C_SPLB_DWIDTH/8) -
PLB
I
1]
-
PLB byte enables
P9 PLB_size[0:3]
PLB
I
-
PLB size of requested transfer
P10 PLB_type[0:2]
PLB
I
-
PLB transfer type
P11 PLB_wrDBus[0: C_SPLB_DWIDTH -
PLB
I
1]
-
PLB write data bus
Unused PLB Slave Interface Input Signals
P12 PLB_UABus[0: 31]
PLB
I
-
PLB upper address bits
P13 PLB_SAValid
PLB
I
-
PLB secondary address valid
P14 _{PLB_rdPrim}
PLB
I
-
PLB secondary to primary read
request indicator
P15 _{PLB_wrPrim}
PLB
I
-
PLB secondary to primary write
request indicator
P16 PLB_abort
PLB
I
-
PLB abort bus request
P17 PLB_busLock
PLB
I
-
PLB bus lock
P18 PLB_MSize
PLB
I
-
PLB data bus width indicator
P19 PLB_lockErr
PLB
I
-
PLB lock error
P20 PLB_wrBurst
PLB
I
-
PLB burst write transfer
P21 PLB_rdBurst
PLB
I
-
PLB burst read transfer
P22 PLB_wrPendReq
PLB
I
-
PLB pending bus write request
P23 PLB_rdPendReq
PLB
I
-
PLB pending bus read request
P24 _{PLB_wrPendPri[0:1]}
PLB
I
-
PLB pending write request
priority
P25 _{PLB_rdPendPri[0:1]}
PLB
I
-
PLB pending read request
priority
P26 PLB_reqPri[0:1]
PLB
I
-
PLB current request priority
P27 PLB_TAttribute[0:15]
PLB
I
-
PLB transfer attribute
PLB Slave Interface Output Signals
P28 Sl_addrAck
PLB
O
0
Slave address acknowledge
P29 Sl_SSize[0:1]
PLB
O
0
Slave data bus size
P30 Sl_wait
PLB
O
0
Slave wait
P31 Sl_rearbitrate
PLB
O
0
Slave bus rearbitrate
P32 Sl_wrDAck
PLB
O
0
Slave write data acknowledge
P33 Sl_wrComp
PLB
O
0
Slave write transfer complete
P34 Sl_rdDBus[0: C_SPLB_DWIDTH - 1] PLB
O
0
Slave read data bus
P35 Sl_rdDAck
PLB
O
0
Slave read data acknowledge
P36 Sl_rdComp
PLB
O
0
Slave read transfer complete
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DS587 December 2, 2009
Product Specification