DS587 Datasheet, PDF (10/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Table 5: XPS ADC Design Parameter - Port Dependencies (Cont’d)
Generic or
Port
Name
Affects Depends
Relationship Description
Sl_MWrErr[0:
P38
C_SPLB_NUM_
MASTERS - 1]
-
G8
Width varies with the size of the PLB
number of masters.
Sl_MRdErr[0:
P39
C_SPLB_NUM_
MASTERS - 1]
-
G8
Width varies with the size of the PLB
number of masters.
Sl_MIRQ[0:
P43
C_SPLB_NUM_MASTE
-
RS - 1]
G8
Width varies with the size of the PLB
number of masters.
XPS ADC Register Descriptions
Table 6 shows the XPS ADC Registers and their addresses.
Table 6: XPS ADC Registers
Base Address + Offset Register Default
(hex)
Name Value (hex)
Access
Register Description
C_BASEADDR + 0x01C
C_BASEADDR + 0x020
GIE
IPISR
0x0
Read/Write
Device Global Interrupt Enable
Register
0x0
Read/TOW ⁽¹⁾ IP Interrupt Status Register
C_BASEADDR + 0x028
IPIER
0x0
Read/Write
IP Interrupt Enable Register
C_BASEADDR + 0x100
C_BASEADDR + 0x104
ADCCR
FIFO
0x0
Read/ Write
ADC Control Register
0x0
Read ⁽²⁾
ADCout Data FIFO
C_BASEADDR + 0x108
OCCY
0x0
Read ⁽²⁾
ADCout Data FIFO Occupancy
Register
1. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the
register to toggle.
2. Writing of a read only register has no effect.
Device Global Interrupt Enable Register (GIE)
The Device Global Interrupt Enable Register provides the final enable/disable for the interrupt output
to the processor and resides in the PLB Interface Module. This is a single bit read/write register as
shown in Figure 4. Table 7 shows the GIE bit definitions.
X-Ref Target - Figure 4
Global Interrupt Enable
Unused
01
Figure 4: Device Global Interrupt Enable Register
31
DS587_04_090809
10
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DS587 December 2, 2009
Product Specification