DS587 Datasheet, PDF (14/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
XPS ADC Timing Diagrams
Figure 9 shows the Timing Diagram for the Read cycle of XPS ADC.
Figure 10 shows the Timing Diagram for the Write cycle of XPS ADC.
X-Ref Target - Figure 9
Cycles
SPLB_Clk
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SPLB_Rst
C_BASEADDR+0x108
C_BASEADDR+0x104
PLB_ABus[0:31]
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
1111
Sl_addrAck
OCCY
1111
ADCout
Sl_rDBus[0:31]
Sl_rdDAck
Figure 9: XPS ADC Read Cycle Timing Diagram
DS587_09_090809
X-Ref Target - Figure 10
Cycles
SPLB_Clk
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SPLB_Rst
C_BASEADDR+0x100
C_BASEADDR+0x20
PLB_ABus[0:31]
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
Sl_addrAck
PLB_wrDBus[0:31]
Sl_wrDAck
1111
ADCCR
1111
IPIER
Figure 10: XPS ADC Write Cycle Timing Diagram
DS587_10_090809
Design Implementation
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE IP Facts
table.
Device Utilization and Performance Benchmarks
Core Performance
Since the XPS ADC core will be used with other design modules in the FPGA, the utilization and timing
numbers reported in this section are estimates only. When the XPS ADC core is combined with other
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DS587 December 2, 2009
Product Specification