DS587 Datasheet, PDF (3/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
interrupts the processor. The FIFO Non-empty interrupt will be set and remains set as long as ADCout
Data FIFO is non-empty.
Delta-Sigma DAC: The Delta-Sigma DAC is a high-speed single bit DAC that uses digital techniques.
Using digital feedback, a string of pulses is generated. The average duty cycle of the pulse string is
proportional to the value of the binary input. The analog signal is created by passing the pulse string
through an analog low-pass filter.
Following standard practice, the Delta-Sigma DAC input (DACin) is an unsigned number with zero
representing the lowest voltage level. The analog voltage output is also positive only. A zero on DACin
produces zero volts at the output. All ones on DACin causes the output to nearly reach V_CCO. For AC
signals, the positive bias on the analog signal can be removed with capacitive coupling to the load.
Though the low pass filter can be driven with any of the Virtex® or Spartan® FPGA Select I/O output
standards that both sink and source current, this design emphasizes the LVTTL standard.
The Delta-Sigma DAC is one bit wider than the ADCout Register. This is required in order for the
lowest numbered bit of the ADCout Register to be significant. When all of the bits have been sampled,
the upper bits of the register feeding the Delta-Sigma DAC is transferred to the ADCout Register.
Figure 2 is a block diagram of a Delta-Sigma DAC. The width of DACin can be configured by changing
the parameter C_DACIN_WIDTH. For simplicity, the block diagram depicts a Delta-Sigma DAC with
a 9-bit DACin. The term “Delta-Sigma” refers to the arithmetic difference and sum, respectively. In this
implementation, binary adders are used to create both the difference and the sum. Although the inputs
to the Delta Adder are unsigned, the outputs of both adders are considered signed numbers. The Delta
Adder calculates the difference between the Delta-Sigma DACin and the current Delta-Sigma DACout.
Because the Delta-Sigma DACout is a single bit, it is “all or nothing”; i.e., either all zeroes or all ones. As
shown in Figure 2, the difference will result when adding the input to a value created by concatenating
two copies of the most significant bit of the Sigma Latch with all zeros. This also compensates for the
fact that Delta-Sigma DACin is unsigned. The Sigma Adder sums its previous output, held in the Sigma
Latch, with the current output of the Delta Adder. Since the Delta Adder sums a value with the upper
two bits as zeroes ({0,0,DACin}) with a value having all but the upper two bits as zeroes ({SL[10],
SL[10], 0,0,0,0,0,0,0,0}), it has a trivial implementation of simply passing through the non-zero bits. No
actual adder is needed.
The interface to VHDL Delta-Sigma DAC module in Figure 2 includes one output and three input
signals as defined in Table 1.
X-Ref Target - Figure 2
{0,0,DACin} ₁₁
11
Delta
11
Adder
Sigma
Adder
11
DQ
Sigma
Latch
SL[10]
D
Q ^DACout
11
{SL[10], SL[10], 0, 0, 0, 0, 0, 0, 0, 0, 0}
SL[10]
Clk (Clock)
Rst (Reset)
DS587_02_090809
Figure 2: Delta-Sigma DAC Internal Block Diagram (C_DACIN_WIDTH = 9)
DS587 December 2, 2009
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Product Specification