DS587 Datasheet, PDF (18/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
X-Ref Target - Figure 12
PLBV46
PLBV46
MiMcriocBrola_Bzlaez®e ^XCL
Processor
XCL
MPMC5
Device Unde
XPS CDMA XPS CDMA _{Test (DUT)}
PowerPC ^® 405
Processor
MC
PPC440
MC DDR2
X-Ref Target - Figure 13
PLBV46
MDM
XPS INTC
XPS BRAM
XPS UART
Lite
MDM
Figure 12: Virtex-5 FX System
DS587_12_0908
MPMC5
Device Under
XPS CDMA XPS CDMA _{Test (DUT)}
MicroBlaze ^®
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
Figure 13: Spartan-3A System
MDM
DS587_13_090809
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately
70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest speed
grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 18.
Table 18: XPS Delta-Sigma ADC Core System Performance
Target FPGA
S3ADSP400 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5FXT70 -1
120
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed
value across all systems.
Specification Exceptions
N/A
18
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DS587 December 2, 2009
Product Specification