DS587 Datasheet, PDF (5/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Sample rate
The XPS ADC sample rate may be expressed as follows:
XPS ADC_SR = f_Clk /(2^{(C_DACIN_WIDTH)} x (FSTM + 1) x (C_DACIN_WIDTH)) samples/second
Conventional Analog to Digital Converters require at least twice the highest input frequency as sample
rate. Delta-Sigma converters require higher f_Clk, so that sufficient number of bit-stream pulses can be
produced. Obviously the more bit-stream pulses can be produced, the better the approximation of the
input signal by the average bit-stream. The average (low pass filtered) bit-stream never exactly
represents the input signal. It is always superimposed with noise. One way to reduce this noise is to
further increase the f_Clk (f_Clk is same as PLB Clock).
Table 2 shows the AnalogIn signal frequency range and ADC sample rate for various PLB Clock
frequencies and FSTM values. Note that the sample rate is dependent on the PLB Clock frequency and
the FSTM value, therefore these should be set appropriately based on the frequency of the AnalogIn
signal to be sampled.
Table 2: XPS ADC Sample Rate Calculation (C_DACIN_WIDTH = 9)
PLB Clock frequency
FSTM loaded
value
AnalogIn signal
frequency range
40 MHz
4
<868 Hz
80 MHz
4
<1736 Hz
100 MHz
4
<2170 Hz
40 MHz
8
<482 Hz
80 MHz
8
<965 Hz
100 MHz
8
<1205 Hz
ADC sample rate
1736 samples/second
3472 samples/second
4340 samples/second
964 samples/second
1929 samples/second
2411 samples/second
XPS ADC I/O Signals
The XPS ADC I/O signals are listed and described in Table 3. All signals are active high.
Table 3: XPS ADC I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 SPLB_Clk
System
I
-
PLB clock
P2 SPLB_Rst
System
I
-
PLB reset
P3 IP2INTC_Irpt
System O
0
Interrupt signal from XPS ADC
PLB Slave Interface Input Signals
P4 PLB_ABus[0: C_SPLB_AWIDTH - 1] PLB
I
-
PLB address bus
P5 PLB_PAValid
PLB
I
-
PLB primary address valid
P6 PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P7 PLB_RNW
PLB
I
-
PLB read not write
DS587 December 2, 2009
www.xilinx.com
5
Product Specification