DS587 Datasheet, PDF (1/20 Pages) Xilinx, Inc – Selectable ADC resolution

DS587 December 2, 2009
XPS Delta-Sigma Analog to
Digital Converter (ADC) (v1.01a)
Product Specification
Introduction
When digital systems are used in real-world
applications, it is often necessary to convert an analog
voltage level to a binary number. The value of this
number is directly or inversely proportional to the
voltage. The analog to digital conversion is realized in
the XPS Delta-Sigma ADC (XPS ADC) using Delta-
Sigma conversion technique. This soft IP core is
designed to interface with the PLB (Processor Local
Bus).
Features
• Connects as a 32-bit slave on PLB V4.6 buses of 32,
64 or 128 bits
• Supports single beat transactions
• Selectable ADC resolution
• 16 entry deep data FIFO
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan^®-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex^®-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6CX
Resources Used
See Table 13, Table 14, Table 15, Table 16, and Table 17.
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Constraints File
EDK TCL Generated
Verification
N/A
Instantiation Template EDK
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.4 or later
Verification
ModelSim PE/SE 6.4b or later
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
© 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are the registered trademarks of IBM Corp. and are used under license. All other trademarks are the property of their
respective owners.
DS587 December 2, 2009
www.xilinx.com
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Product Specification