DS587 Datasheet, PDF (12/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Time characteristics. The width of FSTM value is configurable with the parameter C_FSTM_WIDTH.
For most of the applications a 4-bit value is sufficient. As shown in Figure 6, the ADCCR contains the
EC and FSTM. The bit definitions for ADC Control Register are shown in Table 10.
X-Ref Target - Figure 6
EC
Unused
FSTM
0
27 28
31
DS587_06_090809
Figure 6: ADC Control Register (C_FSTM_WIDTH = 4)
Table 10: ADCout Control Register Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
0
Enable Conversion bit
(EC)
Read/Write ’0’ ^{’1’ = Enabled}
’0’ = Disabled (masked)
1 to [(32-C_
FSTM_WIDTH)-1]
Unused
N/A
0 Unused
[32-C_FSTM_
WIDTH] to 31
Filter Settle Time
Multiplier (FSTM)
These bits hold a binary value which
Read/Write 0 depends on the RC characteristics of
Low pass filter, as described above.
ADCout Data FIFO (FIFO)
This 16 entry deep FIFO contains data to be output by XPS ADC. The ADCout Data FIFO bit definitions
are shown in Table 11. Reading of this location will result in reading a conversion sample from the
FIFO. Software must check for the presence of data before reading. When a read request is issued to an
empty FIFO a bus error will be generated and the result is undefined. Timely reading by software is
required to maintain vacancy in the FIFO for incoming conversions samples. Incoming samples that
encounter a full FIFO are lost. Figure 7 shows the location for data when C_DACIN_WIDTH is set to 9.
X-Ref Target - Figure 7
Unused
ADCout
0
23 24
31
DS587_07_090809
Figure 7: ADCout Data FIFO (C_DACIN_WIDTH = 9)
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DS587 December 2, 2009
Product Specification