DS587 Datasheet, PDF (8/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Table 4: XPS ADC Design Parameters
Generic Feature/Description Parameter Name
Allowable
Values
Default
Value
VHDL Type
System Parameter
G1 Target FPGA family
C_FAMILY
spartan3,
spartan3e,
spartan3a,
spartan3adsp,
aspartan3,
aspartan3e,
aspartan3a,
aspartan3adsp,s
partan6, virtex4,
qvirtex4,
qvvirtex4,
virtex5, virtex5fx,
virtex6, virtex6cx
virtex5
string
PLB Parameters
G2 XPS ADC Base Address C_BASEADDR
Valid Address ⁽¹⁾ None ⁽²⁾ std_logic_vector
G3 XPS ADC High Address C_HIGHADDR
Valid Address ⁽¹⁾ None ⁽²⁾ std_logic_vector
G4 PLB address width
C_SPLB_AWIDTH
32
32
integer
G5 PLB data width
C_SPLB_DWIDTH
32, 64, 128
32
integer
G6
Selects point-to-point or
shared PLB topology
C_SPLB_P2P
0 = Shared Bus
Topology
0
integer
G7
PLB Master ID Bus
Width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_
NUM_MASTERS
) with a minimum
1
value of 1
integer
G8
Number of PLB Masters
C_SPLB_NUM_
MASTERS
1 - 16
1
integer
G9
Width of the Slave Data C_SPLB_NATIVE_
Bus
DWIDTH
32
32
integer
G10 Enable burst support
C_SPLB_SUPPOR
T_BURSTS
0
0
integers
XPS ADC Features
Delta-Sigma DAC input
width. This parameter is
G11
set to one less than the
desired resolution of the
C_DACIN_WIDTH
analog-to-digital
conversion.
9, 11
9
integer
G12
Filter Settle Time
Multiplier(FSTM) width
C_FSTM_WIDTH
4-8
4
integer
1. C_BASEADDR must be a multiple of the range size, where the range size is C_HIGHADDR - C_BASEADDR + 1
and must be a power of two large enough to accommodate all of the registers.
2. No default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler error will
be generated.
8
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DS587 December 2, 2009
Product Specification