DS922 Datasheet, PDF (75/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Table 88: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Boundary-Scan Port Timing Specifications
T_TAPTCK/T_TCKTAP
TMS and TDI setup/hold.
3.0/
2.0
3.0/
2.0
3.0/
2.0
3.0/
2.0
3.0/
2.0
T_TCKTDO
TCK falling edge to TDO output.
F_TCK
TCK frequency.
BPI Master Flash Mode Programming Switching
7
7
7
7
7
66
66
66
66
66
T_BPICCO
A[28:00], RS[1:0], FCS_B, FOE_B,
FWE_B, ADV_B clock to out.
10
10
10
10
10
T_BPIDCC/T_BPICCD
D[15:00] setup/hold.
SPI Master Flash Mode Programming Switching
3.5/0 3.5/0 3.5/0 4.0/0 4.0/0
T_SPIDCC/T_SPICCD
D[03:00] setup/hold.
T_SPIDCC/T_SPICCD
D[07:04] setup/hold.
T_SPICCM
MOSI clock to out.
T_SPICCFC
FCS_B clock to out.
DNA Port Switching
3.0/0
3.5/0
8.0
8.0
3.0/0
3.5/0
8.0
8.0
3.0/0
3.5/0
8.0
8.0
3.5/0
4.0/0
8.0
8.0
3.5/0
4.0/0
8.0
8.0
F_DNACK
DNA port frequency.
STARTUPE3 Ports
200 200 200 175 175
T_USRCCLKO
STARTUPE3 USRCCLKO input port to
CCLK pin output delay.
1.00/ 1.00/ 1.00/ 1.00/ 1.00/
6.00 6.70 7.50 7.50 7.50
T_DO
DO[3:0] ports to D03-D00 pins output
delay.
1.00/ 1.00/ 1.00/ 1.00/ 1.00/
6.70 7.70 8.40 8.40 8.40
T_DTS
DTS[3:0] ports to D03-D00 pins 3-state 1.00/ 1.00/ 1.00/ 1.00/ 1.00/
delays.
7.30 8.30 9.00 9.00 9.00
T_FCSBO
FCSBO port to FCS_B pin output delay.
1.00/ 1.00/ 1.00/ 1.00/ 1.00/
6.90 8.00 8.60 8.60 8.60
T_FCSBTS
FCSBTS port to FCS_B pin 3-state delay.
1.00/
6.90
1.00/
8.00
1.00/
8.60
1.00/
8.60
1.00/
8.60
T_USRDONEO
USRDONEO port to DONE pin output
delay.
1.00/ 1.00/ 1.00/ 1.00/ 1.00/
8.50 9.60 10.40 10.40 10.40
T_USRDONETS
USRDONETS port to DONE pin 3-state
delay.
1.00/ 1.00/ 1.00/ 1.00/ 1.00/
8.50 9.60 10.40 10.40 10.40
T_DI
D03-D00 pins to DI[3:0] ports input
delay.
0.5/
2.6
0.5/
3.1
0.5/
3.5
0.5/
3.5
0.5/
3.5
F_CFGMCLK
F_CFGMCLKTOL
STARTUPE3 CFGMCLK output frequency.
STARTUPE3 CFGMCLK output frequency
tolerance.
50
±15
50
±15
50
±15
50
±15
50
±15
T_{DCI_MATCH}
Specifies a stall in the startup cycle until
the digitally controlled impedance (DCI)
4
4
4
4
4
match signals are asserted.
Units
ns, Min
ns, Max
MHz, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Max
ns, Max
MHz, Max
ns, Min/Max
ns, Min/Max
ns, Min/Max
ns, Min/Max
ns, Min/Max
ns, Min/Max
ns, Min/Max
ns, Min/Max
MHz, Typ
%, Max
ms, Max
Notes:
1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this
duty-cycle requirement.
DS922 (v1.1) May 9, 2016
Advance Product Specification
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