DS922 Datasheet, PDF (15/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Table 14: Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks⁽¹⁾
I/O Standard
Min
V_ICM (V)⁽²⁾
Typ
Max
V_ID (V)⁽³⁾
Min Max
V_OL (V)⁽⁴⁾
Max
V_OH (V)⁽⁵⁾
Min
I_OL I_OH
mA mA
DIFF_HSTL_I
0.680
V_CCO/2 (V_CCO/2) + 0.150 0.100 –
0.400
V_CCO – 0.400
5.8 –5.8
DIFF_HSTL_I_12
0.400 x V_CCO V_CCO/2 0.600 x V_CCO 0.100 –
0.250 x V_CCO
0.750 x V_CCO
4.1 –4.1
DIFF_HSTL_I_18 (V_CCO/2) – 0.175 V_CCO/2 (V_CCO/2) + 0.175 0.100 –
0.400
V_CCO – 0.400
6.2 –6.2
DIFF_HSUL_12
(V_CCO/2) – 0.120 V_CCO/2 (V_CCO/2) + 0.120 0.100 –
20% V_CCO
80% V_CCO
0.1 –0.1
DIFF_SSTL12
(V_CCO/2) – 0.150 V_CCO/2 (V_CCO/2) + 0.150 0.100 – (V_CCO/2) – 0.150 (V_CCO/2) + 0.150 8.0 –8.0
DIFF_SSTL135
(V_CCO/2) – 0.150 V_CCO/2 (V_CCO/2) + 0.150 0.100 – (V_CCO/2) – 0.150 (V_CCO/2) + 0.150 9.0 –9.0
DIFF_SSTL15
(V_CCO/2) – 0.175 V_CCO/2 (V_CCO/2) + 0.175 0.100 – (V_CCO/2) – 0.175 (V_CCO/2) + 0.175 10.0 –10.0
DIFF_SSTL18_I (V_CCO/2) – 0.175 V_CCO/2 (V_CCO/2) + 0.175 0.100 – (V_CCO/2) – 0.470 (V_CCO/2) + 0.470 7.0 –7.0
Notes:
1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 15, Table 16, and Table 17.
2. V_ICM is the input common mode voltage.
3. V_ID is the input differential voltage.
4. V_OL is the single-ended low-output voltage.
5. V_OH is the single-ended high-output voltage.
Table 15: DC Input Levels for Differential POD10 and POD12 I/O Standards⁽¹⁾⁽²⁾
I/O Standard
Min
V_ICM (V)
Typ
Max
Min
V_ID (V)
DIFF_POD10
0.63
0.70
0.77
0.14
DIFF_POD12
0.76
0.84
0.92
0.16
Max
–
–
Notes:
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).
Table 16: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards⁽¹⁾⁽²⁾
Symbol
R_OL
R_OH
Description
Pull-down resistance.
Pull-up resistance.
V_OUT
V_{OM_DC} (as described in Table 17)
V_{OM_DC} (as described in Table 17)
Min
36
36
Typ
40
40
Max
44
44
Units
Ω
Ω
Notes:
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).
Table 17: Table 16 Definitions for DC Output Levels for POD Standards
Symbol
Description
All Speed Grades
V_{OM_DC}
DC output Mid measurement level (for IV curve linearity).
0.8 x V_CCO
Units
V
DS922 (v1.1) May 9, 2016
Advance Product Specification
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