DS922 Datasheet, PDF (69/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Integrated Interface Block for Interlaken
More information and documentation on solutions using the integrated interface block for Interlaken can
be found at UltraScale Interlaken. The UltraScale Architecture and Product Overview (DS890) lists how
many blocks are in each Kintex UltraScale+ FPGA.
Table 82: Maximum Performance for Interlaken Designs
Symbol
Description
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3⁽¹⁾
-2⁽¹⁾
-1
-2⁽¹⁾
-1
F_{RX_SERDES_CLK}
Receive serializer/
deserializer clock
440.79
440.79
195.32
195.32
161.14 MHz
Transmit
F_{TX_SERDES_CLK} serializer/
deserializer clock
440.79
440.79
195.32
195.32
161.14 MHz
F_{DRP_CLK}
Dynamic
reconfiguration
port clock
250.00
250.00
250.00
250.00
250.00 MHz
Min Max Min Max Min Max Min Max Min Max
F_{CORE_CLK}
Interlaken core
clock
300.00⁽²⁾
460.00⁽³⁾
300.00⁽²⁾
460.00⁽³⁾
300.00⁽²⁾
MHz
300.00 322.27
429.69 300.00 322.27
412.50⁽³⁾
MHz
F_{LBUS_CLK}
Interlaken local
bus clock
300.00 349.52 300.00 349.52 300.00 322.27 300.00 349.52 300.00 322.27 MHz
Notes:
1. Kintex UltraScale+ FPGAs in the SFVB784, FFVA676, and FFVA1156 packages are only supported using the 12 x 12.5G
Interlaken configuration. See Table 67 for the F_GTYMAX description.
2. The minimum value for CORE_CLK is 300 MHz for the 12 x 12.5G Interlaken configuration.
3. The minimum value for CORE_CLK is 412.5 MHz for the 6 x 25.78125G Interlaken configuration.
DS922 (v1.1) May 9, 2016
Advance Product Specification
www.xilinx.com
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