DS922 Datasheet, PDF (34/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 32: Block RAM and FIFO Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Maximum Frequency
F_{MAX_WF_NC}
Block RAM
(WRITE_FIRST and NO_CHANGE modes).
825
737
645
585
516
F_{MAX_RF}
F_{MAX_FIFO}
F_{MAX_ECC}
Block RAM (READ_FIRST mode).
FIFO in all modes without ECC.
Block RAM and FIFO in ECC configuration
without PIPELINE.
Block RAM and FIFO in ECC configuration
with PIPELINE and Block RAM in
WRITE_FIRST or NO_CHANGE mode.
718
637
575
510
460
825
737
645
585
516
718
637
575
510
460
825
737
645
585
516
T_PW(1)
Minimum pulse width.
Block RAM and FIFO Clock-to-Out Delays
495
542
543
577
578
T_{RCKO_DO}
Clock CLK to DOUT output (without output
register).
0.92
1.03
1.11
1.46
1.54
T_{RCKO_DO_REG}
Clock CLK to DOUT output (with output
register).
0.27
0.29
0.31
0.42
0.44
Units
MHz
MHz
MHz
MHz
MHz
ps
ns,
Max
ns,
Max
Notes:
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher
frequencies.
DS922 (v1.1) May 9, 2016
Advance Product Specification
www.xilinx.com
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