DS922 Datasheet, PDF (25/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Table 28: IOB High Performance (HP) Switching Characteristics
I/O Standards
T_{INBUF_DELAY_PAD_I}
0.90V 0.85V
0.72V
T_{OUTBUF_DELAY_O_PAD}
0.90V 0.85V
0.72V
T_{OUTBUF_DELAY_TD_PAD}
0.90V 0.85V
0.72V
Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
DIFF_HSTL_I_12_F
0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns
DIFF_HSTL_I_12_M
0.277 0.335 0.342 0.335 0.321 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns
DIFF_HSTL_I_12_S
0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns
DIFF_HSTL_I_18_F
0.285 0.314 0.334 0.314 0.328 0.388 0.396 0.413 0.396 0.388 0.388 0.396 0.413 0.396 0.388 ns
DIFF_HSTL_I_18_M
0.285 0.314 0.334 0.314 0.328 0.388 0.393 0.413 0.393 0.389 0.388 0.393 0.413 0.393 0.389 ns
DIFF_HSTL_I_18_S
0.285 0.314 0.334 0.314 0.328 0.388 0.394 0.413 0.391 0.387 0.388 0.394 0.413 0.391 0.387 ns
DIFF_HSTL_I_DCI_12_F 0.277 0.335 0.342 0.335 0.321 0.422 0.420 0.444 0.421 0.414 0.422 0.420 0.444 0.421 0.414 ns
DIFF_HSTL_I_DCI_12_M 0.277 0.335 0.342 0.335 0.321 0.422 0.420 0.444 0.422 0.412 0.422 0.420 0.444 0.422 0.412 ns
DIFF_HSTL_I_DCI_12_S 0.277 0.335 0.342 0.335 0.321 0.422 0.421 0.442 0.421 0.412 0.422 0.421 0.442 0.421 0.412 ns
DIFF_HSTL_I_DCI_18_F 0.284 0.314 0.331 0.314 0.331 0.418 0.425 0.440 0.424 0.417 0.418 0.425 0.440 0.424 0.417 ns
DIFF_HSTL_I_DCI_18_M 0.284 0.314 0.331 0.314 0.331 0.418 0.424 0.443 0.423 0.416 0.418 0.424 0.443 0.423 0.416 ns
DIFF_HSTL_I_DCI_18_S 0.284 0.314 0.331 0.314 0.331 0.418 0.424 0.443 0.424 0.417 0.418 0.424 0.443 0.424 0.417 ns
DIFF_HSTL_I_DCI_F
0.294 0.313 0.330 0.313 0.320 0.420 0.423 0.438 0.421 0.415 0.420 0.423 0.438 0.421 0.415 ns
DIFF_HSTL_I_DCI_M
0.294 0.313 0.330 0.313 0.320 0.420 0.423 0.440 0.423 0.416 0.420 0.423 0.440 0.423 0.416 ns
DIFF_HSTL_I_DCI_S
0.294 0.313 0.330 0.313 0.320 0.420 0.421 0.440 0.417 0.414 0.420 0.421 0.440 0.417 0.414 ns
DIFF_HSTL_I_F
0.295 0.330 0.341 0.330 0.320 0.393 0.391 0.411 0.394 0.385 0.393 0.391 0.411 0.394 0.385 ns
DIFF_HSTL_I_M
0.295 0.330 0.341 0.330 0.320 0.392 0.393 0.413 0.397 0.386 0.392 0.393 0.413 0.397 0.386 ns
DIFF_HSTL_I_S
0.295 0.330 0.341 0.330 0.320 0.393 0.393 0.413 0.394 0.384 0.393 0.393 0.413 0.394 0.384 ns
DIFF_HSUL_12_DCI_F 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns
DIFF_HSUL_12_DCI_M 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns
DIFF_HSUL_12_DCI_S 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns
DIFF_HSUL_12_F
0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns
DIFF_HSUL_12_M
0.277 0.335 0.342 0.335 0.321 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns
DIFF_HSUL_12_S
0.277 0.335 0.342 0.335 0.321 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns
DIFF_POD10_DCI_F
0.286 0.325 0.340 0.325 0.334 0.438 0.431 0.451 0.431 0.418 0.438 0.431 0.451 0.431 0.418 ns
DIFF_POD10_DCI_M
0.286 0.325 0.340 0.325 0.334 0.592 0.627 0.660 0.627 0.622 0.592 0.627 0.660 0.627 0.622 ns
DIFF_POD10_DCI_S
0.286 0.325 0.340 0.325 0.334 0.823 0.900 0.974 0.900 0.888 0.823 0.900 0.974 0.900 0.888 ns
DIFF_POD10_F
0.277 0.314 0.331 0.314 0.317 0.412 0.406 0.426 0.406 0.392 0.412 0.406 0.426 0.406 0.392 ns
DIFF_POD10_M
0.277 0.314 0.331 0.314 0.317 0.570 0.593 0.627 0.593 0.588 0.570 0.593 0.627 0.593 0.588 ns
DIFF_POD10_S
0.277 0.314 0.331 0.314 0.317 0.800 0.853 0.914 0.853 0.835 0.800 0.853 0.914 0.853 0.835 ns
DIFF_POD12_DCI_F
0.275 0.314 0.333 0.314 0.318 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns
DIFF_POD12_DCI_M
0.275 0.314 0.333 0.314 0.318 0.586 0.628 0.662 0.628 0.623 0.586 0.628 0.662 0.628 0.623 ns
DIFF_POD12_DCI_S
0.275 0.314 0.333 0.314 0.318 0.813 0.899 0.959 0.899 0.892 0.813 0.899 0.959 0.899 0.892 ns
DIFF_POD12_F
0.275 0.323 0.341 0.323 0.316 0.402 0.396 0.414 0.395 0.383 0.402 0.396 0.414 0.395 0.383 ns
DIFF_POD12_M
0.275 0.323 0.341 0.323 0.316 0.562 0.595 0.629 0.595 0.589 0.562 0.595 0.629 0.595 0.589 ns
DIFF_POD12_S
0.275 0.323 0.341 0.323 0.316 0.789 0.844 0.899 0.844 0.835 0.789 0.844 0.899 0.844 0.835 ns
DIFF_SSTL12_DCI_F
0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns
DIFF_SSTL12_DCI_M 0.283 0.327 0.344 0.327 0.317 0.584 0.630 0.664 0.628 0.624 0.584 0.630 0.664 0.628 0.624 ns
DIFF_SSTL12_DCI_S
0.283 0.327 0.344 0.327 0.317 0.813 0.899 0.959 0.899 0.892 0.813 0.899 0.959 0.899 0.892 ns
DIFF_SSTL12_F
0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns
DIFF_SSTL12_M
0.277 0.335 0.342 0.335 0.321 0.561 0.597 0.631 0.597 0.591 0.561 0.597 0.631 0.597 0.591 ns
DS922 (v1.1) May 9, 2016
Advance Product Specification
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