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DS922 Datasheet, PDF (48/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics
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Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Table 54: GTH Transceiver User Clock Switching Characteristics(1)
Symbol
Description
Data Width Conditions
(Bit)
Speed Grade, Temperature Ranges, and
VCCINT Operating Voltages
0.90V
0.85V
0.72V
Units
Internal Interconnect
Logic
Logic
-3(2)
-2(2)(3)
-1(4)
-2(3) -1(3)(5)
FTXOUTPMA
TXOUTCLK maximum frequency sourced
from OUTCLKPMA
511.719 511.719 390.625 390.625 322.266 MHz
FRXOUTPMA
RXOUTCLK maximum frequency sourced
from OUTCLKPMA
511.719 511.719 390.625 390.625 322.266 MHz
FTXOUTPROGDIV
TXOUTCLK maximum frequency sourced
from TXPROGDIVCLK
511.719 511.719 511.719 511.719 511.719 MHz
FRXOUTPROGDIV
RXOUTCLK maximum frequency sourced
from RXPROGDIVCLK
511.719 511.719 511.719 511.719 511.719 MHz
FTXIN
16
TXUSRCLK
32
maximum
frequency
20
40
16, 32
32, 64
20, 40
40, 80
511.719 511.719 390.625 390.625 322.266
511.719 511.719 390.625 390.625 322.266
409.375 409.375 312.500 312.500 257.813
409.375 409.375 312.500 312.500 257.813
MHz
MHz
MHz
MHz
FRXIN
16
RXUSRCLK
32
maximum
frequency
20
40
16, 32
32, 64
20, 40
40, 80
511.719 511.719 390.625 390.625 322.266
511.719 511.719 390.625 390.625 322.266
409.375 409.375 312.500 312.500 257.813
409.375 409.375 312.500 312.500 257.813
MHz
MHz
MHz
MHz
16
16
511.719 511.719 390.625 390.625 322.266 MHz
16
32
255.859 255.859 195.313 195.313 161.133 MHz
FTXIN2
32
TXUSRCLK2
32
maximum
frequency
20
20
32
511.719 511.719 390.625 390.625 322.266 MHz
64
255.859 255.859 195.313 195.313 161.133 MHz
20
409.375 409.375 312.500 312.500 257.813 MHz
40
204.688 204.688 156.250 156.250 128.906 MHz
40
40
409.375 409.375 312.500 312.500 257.813 MHz
40
80
204.688 204.688 156.250 156.250 128.906 MHz
16
16
511.719 511.719 390.625 390.625 322.266 MHz
16
32
255.859 255.859 195.313 195.313 161.133 MHz
FRXIN2
32
RXUSRCLK2
32
maximum
frequency
20
20
32
511.719 511.719 390.625 390.625 322.266 MHz
64
255.859 255.859 195.313 195.313 161.133 MHz
20
409.375 409.375 312.500 312.500 257.813 MHz
40
204.688 204.688 156.250 156.250 128.906 MHz
40
40
409.375 409.375 312.500 312.500 257.813 MHz
40
80
204.688 204.688 156.250 156.250 128.906 MHz
Notes:
1. Clocking must be implemented as described in UltraScale Architecture GTH Transceiver User Guide (UG576).
2. For speed grades -3E and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.
3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when
VCCINT = 0.85V or 6.25 Gb/s when VCCINT = 0.72V.
4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.
5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when
VCCINT = 0.85V or 5.15625 Gb/s when VCCINT = 0.72V.
DS922 (v1.1) May 9, 2016
Advance Product Specification
www.xilinx.com
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