DS922 Datasheet, PDF (47/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Table 51: GTH Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Min
Typ
Max
F_GCLK
T_RCLK
T_FCLK
T_DCREF
Reference clock frequency range.
60
Reference clock rise time.
20% – 80%
–
Reference clock fall time.
80% – 20%
–
Reference clock duty cycle.
Transceiver PLL only
40
–
820
200
–
200
–
50
60
X-Ref Target - Figure 5
80%
T_RCLK
Units
MHz
ps
ps
%
20%
T_FCLK
ds922_05_080415
Figure 5: Reference Clock Timing Parameters
Table 52: GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask
Symbol
Description
Offset
Frequency
Min
Typ
Max
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–105
QPLL_{REFCLKMASK(1)(2)} phase noise mask at
REFCLK frequency = 312.5 MHz.
100 kHz
–
–
–124
1 MHz
–
–
–130
10 kHz
–
–
–105
CPLL_{REFCLKMASK(1)(2)}
CPLL reference clock select phase noise ^{100 kHz}
mask at REFCLK frequency = 312.5 MHz. _{1 MHz}
–
–
–
–124
–
–130
50 MHz
–
–
–140
Units
dBc/Hz
dBc/Hz
Notes:
1. For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 x Log(N/312.5) where N
is the new reference clock frequency in MHz.
2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a
supported protocol, e.g., PCIe.
Table 53: GTH Transceiver PLL/Lock Time Adaptation
Symbol
Description
Conditions
T_LOCK
T_DLOCK
Initial PLL lock.
Clock recovery phase acquisition and
adaptation time for decision
feedback equalizer (DFE).
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
After the PLL is locked to
the reference clock, this is
the time it takes to lock
the clock data recovery
(CDR) to the data present
at the input.
All Speed Grades
Min
Typ
Max
–
–
1
–
–
Units
ms
UI
UI
DS922 (v1.1) May 9, 2016
Advance Product Specification
www.xilinx.com
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