DS922 Datasheet, PDF (61/77 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
Table 72: GTY Transceiver User Clock Switching Characteristics⁽¹⁾
Symbol
Data Width Conditions
Description
(Bit)
0.90V
Speed Grade and
V_CCINT Operating Voltages
0.85
0.72
Units
Internal Interconnect
Logic
Logic
-3
-2
-1
-2
-1
F_TXOUTPMA
TXOUTCLK maximum frequency sourced
from OUTCLKPMA
511.719 511.719 390.625 511.719 322.266
MHz
F_RXOUTPMA
RXOUTCLK maximum frequency sourced
from OUTCLKPMA
511.719 511.719 390.625 511.719 322.266
MHz
F_TXOUTPROGDIV
TXOUTCLK maximum frequency sourced
from TXPROGDIVCLK
511.719 511.719 511.719 511.719 511.719
MHz
F_RXOUTPROGDIV
RXOUTCLK maximum frequency sourced
from RXPROGDIVCLK
511.719 511.719 511.719 511.719 511.719
MHz
16
16, 32
511.719 511.719 390.625 390.625 322.266 MHz
F_TXIN
32
TXUSRCLK
64
maximum
frequency
20
40
32, 64
64, 128
20, 40
40, 80
511.719
511.719
409.375
409.375
511.719
440.781
409.375
409.375
390.625
195.313
312.500
312.500
390.625
402.813
312.500
350.000
322.266
195.313
312.500
257.813
MHz
MHz
MHz
MHz
80
80, 160
409.375 352.625 156.250 352.625 156.250 MHz
16
16, 32
511.719 511.719 390.625 390.625 322.266 MHz
F_RXIN
32
RXUSRCLK
64
maximum
frequency
20
40
32, 64
64, 128
20, 40
40, 80
511.719
511.719
409.375
409.375
511.719
440.781
409.375
409.375
390.625
195.313
312.500
312.500
390.625
402.813
312.500
350.000
322.266
195.313
312.500
257.813
MHz
MHz
MHz
MHz
80
80, 160
409.375 352.625 156.250 352.625 156.250 MHz
16
16, 32
511.719 511.719 390.625 390.625 322.266 MHz
F_TXIN2
32
TXUSRCLK2
64
maximum
frequency
20
40
32, 64
64, 128
20, 40
40, 80
511.719
511.719
409.375
409.375
511.719
440.781
409.375
409.375
390.625
195.313
312.500
312.500
390.625
402.813
312.500
350.000
322.266
195.313
312.500
257.813
MHz
MHz
MHz
MHz
80
80, 160
409.375 352.625 156.250 352.625 156.250 MHz
16
16, 32
511.719 511.719 390.625 390.625 322.266 MHz
F_RXIN2
32
RXUSRCLK2
64
maximum
frequency
20
40
32, 64
64, 128
20, 40
40, 80
511.719
511.719
409.375
409.375
511.719
440.781
409.375
409.375
390.625
195.313
312.500
312.500
390.625
402.813
312.500
350.000
322.266
195.313
312.500
257.813
MHz
MHz
MHz
MHz
80
80, 160
409.375 352.625 156.250 352.625 156.250 MHz
Notes:
1. Clocking must be implemented as described in the UltraScale Architecture GTY Transceiver User Guide (UG578).
DS922 (v1.1) May 9, 2016
Advance Product Specification
www.xilinx.com
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