W83637HF Datasheet, PDF (98/149 Pages) Winbond – LPC I/O

W83637HF
Bit 0: Warm reset. Setting "1" to this bit pulls down SCRST#. SCCLK is stopped, SCIO in input
mode and SCLED is inactive. ECR's SCIODIR, SCKFS1 and SCKFS0 control bits and control
bits in CBR, GTR, BLH and BLL are cleared to default values. User must write a "0" to this bit
to recover to normal state. This bit is similar to cold reset except SCPWR# stays active low.
Baud rate divisor Latch Lower byte (BLL at base address + 0 when BDLAB = 1, default 1Fh)
This register combining with BLH and CBR determine internal sampling clock frequency. Refer to
section 2.2.8 for example.
7 6 5 4 32 1 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh.
Baud rate divisor Latch Higher byte (BLH at base address + 1 when BDLAB = 1, default 00h)
This register combining with BLL and CBR determine internal sampling clock frequency. Refer to
section 2.2.8 for example.
7 6 5 4 32 1 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h.
- 93 -
Publication Release Date: June 25, 2003
Revision 1.3