W83637HF Datasheet, PDF (94/149 Pages) Winbond – LPC I/O

W83637HF
Smart Card Control Register (SCCR at base address + 3)
In contrast to its UART counterpart, Smart Card Control Register only controls parity bit setting
because data length is fixed at 8-bit long for Smart Card interface protocol.
7 6 5 4 32 1 0
Reserved
Reserved
Reserved
PBE
EPE
Reserved
Reserved
BDLAB
Bit 7: BDLAB means baud rate divisor latch access bit. When this bit is set to a logical "1", users may
access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of
baudrate generator during a read/write operation. A special Smart Card ID can also be read at
base address + 2 when BDLAB is "1". When this bit is set to "0", accesses to base address +
0, 1 or 2 refer to RBR/TBR, IER or ISR/SCFR respectively.
Bit 6 ~ 5: Reserved.
Bit 4: EPE means even parity enable. This bit is only available when bit 3 of SCCR is programmed to
"1". It prescribes number of logical 1s in a data word including parity bit. When this bit is set
to "1", even parity is required for transmission and reception. Odd parity is demanded when
this bit is set to "0".
Bit 3: PBE means parity bit enable. When this bit is set, a parity bit is inserted between last data bit
and stop bit for transmission integrity check.
Bit 2 ~ 0: Reserved.
- 89 -
Publication Release Date: June 25, 2003
Revision 1.3