W83637HF Datasheet, PDF (95/149 Pages) Winbond – LPC I/O

W83637HF
Clock Base Register (CBR at base address + 4, default 0Ch)
This register combining with BLH and BLL (baud rate latches) determine internal sampling clock
frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh which mean
SCCLK clock frequency is 372 (12 x 31) times of internal sampling clock frequency. The default
values of CBR, BLH and BLL are corresponding to default values of transmission factors F and D
specified in ISO/IEC 7816-3. The value of 0Ch of CBR means there're 12 sampling clock pulses to
detect a 1-etu (elementary time unit) data bit on SCIO signal. It is recommended that user sets CBR
to be around 16 to maintain better data integrity and transmission stability.
7 6 5 4 32 1 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 7 ~ 0: Clock base value. It specifies number of internal sampling clock pulses for a data bit.
Default to be 0Ch.
Smart Card Status Register (SCSR at base address + 5)
This 8-bit register provides information about status of data transfer during communication.
7 6 5 4 32 1 0
RDR
OER
PBER
NSER
SBD
TBRE
TSRE
RxFEI
Bit 7: RxFEI means receiver FIFO error indication. This bit is set to "1" when there is at least one
parity bit error, no stop bit error or silent byte detected error in receiver FIFO. It is cleared by
reading from SCSR if there is no remaining error left in receiver FIFO.
Bit 6: TSRE means transmitter shift register empty. This bit is set to "1" when transmitter shift register
is empty.
Bit 5: TBRE means transmitter buffer register empty. In non-FIFO mode, this bit will be set to a logical
1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt
is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1"
when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or
FIFO.
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Publication Release Date: June 25, 2003
Revision 1.3