|
W83637HF Datasheet, PDF (88/149 Pages) Winbond – LPC I/O | |||
|
◁ |
W83637HF
Note:
Abbreviation explanation (in alphabetical order) â
BDLAB â Baud rate divisor latch access bit.
CLKSTP â Stop Smart Card interface's clock SCCLK.
CLKSTPL â Set SCCLK level when CLKSTP is "1".
EPE â Even parity enable.
ERDRI â Enable RBR (Receiver Buffer Register) data ready interrupt.
ESCPTI - Enable SCPSNT interrupt.
ESCSRI - Enable interrupts of SCSR (read only Smart Card Status Register at base address + 5)
events.
ETBREI â Enable TBR (write only Transmitter Buffer Register at base address + 0) empty interrupt.
INTS2 ~ INTS0 â Interrupt status bits. Refer to description of ISR (read only Interrupt Status Register
at base address + 2) for details.
NSER â No stop bit error.
OER â Overrun error.
PBE â Parity bit enable.
PBER â Parity bit error.
RDR â Receiver data ready status.
RxFEI â Receiver FIFO error indication.
RxFRST â Receiver FIFO reset.
RxTL1 ~ RxTL0 â Receiver threshold level setting bits. Refer to description of SCFR (write only
Smart Card FIFO control register at base address + 2) for details.
SBD â Silent byte detected.
SCIODIR â SCIO direction bit (0/1 mean output/input respectively).
SCKFS1 ~ SCKFS0 â Smart Card interface clock frequency selection bits. Refer to description of
ECR (Extended Control Register at base address + 7) for details.
SCPTI â SCPSNT toggle interrupt status.
SC_SEL â Smart Card socket selection.
TBRE â TBR (write only Transmitter Buffer Register at base address + 0) empty status.
TSRE â TSR (Transmitter shift register) empty status.
TxFRST â Transmitter FIFO reset.
- 83 -
Publication Release Date: June 25, 2003
Revision 1.3
|
▷ |