W83637HF Datasheet, PDF (97/149 Pages) Winbond – LPC I/O

W83637HF
Extended Control Register (ECR at base address + 7, default 12h)
This register contains reset control bits, clock frequency selection bits, clock stop control bits and SCIO
direction control bit.
7 6 5 4 32 1 0
Warm reset
SCIODIR
CLKSTP
CLKSTPL
SCKFS0
SCKFS1
Reserved
Cold reset
Bit 7: Cold reset. Setting "1" to this bit turns off power to Smart Card interface by pulling up SCPWR#.
SCCLK is stopped, SCRST# kept low, SCIO in input mode and SCLED is inactive. ECR's
SCIODIR, SCKFS1 and SCKFS0 control bits and control bits in CBR, GTR, BLH and BLL are
cleared to default values. User must write a "0" to this bit to recover to normal state.
Bit 6: Reserved.
Bit 5, 4: SCKFS1 and SCKFS0 means SCCLK frequency selection bit 1 and 0. They selects working
clock frequency as following table. Default values are 01h.
SCKFS1, SCKFS0
00
01
10
11
SCCLK frequency
1.5 MHz
3.0 MHz
6.0 MHz
12 MHz
Bit 3: CLKSTP means clock stop control bit. Setting "1" to this bit stops SCCLK at a voltage level
specified by CLKSTPL (bit 2 of ECR).
Bit 2: CLKSTPL means clock stop voltage level.
=0
SCCLK stops at low if CLKSTP is also set to "1".
=1
SCCLK stops at high if CLKSTP is also set to "1".
Bit 1: SDIODIR means SDIO direction.
=0
SDIO is in output mode.
=1
SDIO is in input mode.
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Publication Release Date: June 25, 2003
Revision 1.3