W83637HF Datasheet, PDF (93/149 Pages) Winbond – LPC I/O

W83637HF
Smart Card FIFO control Register (SCFR at base address + 2 when BDLAB = 0, write only)
This register controls FIFO function of Smart Card interface.
7 6 5 4 32 1 0
Enable FIFO
RxFRST
TxFRST
Reserved
Reserved
Reserved
RxTL0
RxTL1
Bit 7, 6: RxTL1 and RxTL0 mean receiver FIFO active threshold level control bits. These two bits are
used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active
level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an
interrupt is activated to notify host to read data from FIFO. Default to be 00b.
RxTL1
0
0
1
1
RxTL0
0
1
0
1
Rx FIFO Interrupt Active Level (Bytes)
01
04
08
14
Bit 5 ~ 3: Reserved.
Bit 2: TxFRST means transmitter FIFO reset control bit. Setting this bit to a logical "1" resets the
transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1".
Default is "0".
Bit 1: RxFRST means receiver FIFO reset control bit. Setting this bit to a logical "1" resets the
receiver FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1".
Default is "0".
Bit 0: This bit enables FIFO of Smart Card interface. It should be set to a logical "1" before other bits
of SCFR are programmed. Default is "0".
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Publication Release Date: June 25, 2003
Revision 1.3