W632GG8KB Datasheet, PDF(93/159 Page) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

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W632GG8KB Datasheet, PDF (93/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

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W632GG8KB

8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods

If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap (see Figure 86). In

this case, the response of the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD

entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period).

If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case the response of the DDR3 SDRAMs RTT

to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD exit transition period to the end of the PD entry

transition period. Note that in the bottom part of Figure 86 it is assumed that there was no Refresh command in progress when Idle state was entered.

T10

T11

T12

T13

T14

CK#

Command

REF

NOP

CKE

tANPD

tRFC(min)

PD entry transition period

PD exit transition period

tANPD

short CKE low transition period

tXPDLL

CKE

tANPD

short CKE high transition period

tXPDLL

TIME BREAK

TRANSITIONING

DON'T CARE

Figure 86 â Transition period for short CKE cycles, entry and exit period overlapping (AL = 0, WL = 5, tANPD = WL - 1 = 4)

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Publication Release Date: Dec. 08, 2014

Revision: A04

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