W632GG8KB Datasheet, PDF (116/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
10.10 ODT Timing Definitions
10.10.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 98.
VDDQ
CK, CK#
DQ, DM
DUT DQS, DQS#
TDQS, TDQS#
RTT = 25Ω
VTT = VSSQ
VSSQ
Timing reference point
Figure 98 – ODT Timing Reference Load
10.10.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 37 and subsequent figures.
Measurement reference settings are provided in Table 38.
Table 37 – ODT Timing Definitions
Symbol
tAON
tAONPD
tAOF
tAOFPD
tADC
Begin Point Definition
Rising edge of CK - CK# defined by the end
point of ODTLon
Rising edge of CK - CK# with ODT being first
registered high
Rising edge of CK - CK#defined by the end
point of ODTLoff
Rising edge of CK - CK# with ODT being first
registered low
Rising edge of CK - CK# defined by the end
point of ODTLcnw, ODTLcwn4 or ODTLcwn8
End Point Definition
Extrapolated point at VSSQ
Extrapolated point at VSSQ
End point: Extrapolated point at VRtt_Nom
End point: Extrapolated point at VRtt_Nom
End point: Extrapolated point at VRtt_WR and
VRtt_Nom respectively
Figure
Figure 99
Figure 100
Figure 101
Figure 102
Figure 103
Table 38 – Reference Settings for ODT Timing Measurements
Measured Parameter
tAON
tAONPD
tAOF
tAOFPD
tADC
Rtt_Nom Setting
RZQ/4
RZQ/12
RZQ/4
RZQ/12
RZQ/4
RZQ/12
RZQ/4
RZQ/12
RZQ/12
Rtt_WR Setting
NA
NA
NA
NA
NA
NA
NA
NA
RZQ/2
VSW1 [V]
0.05
0.10
0.05
0.10
0.05
0.10
0.05
0.10
0.20
VSW2 [V]
0.10
0.20
0.10
0.20
0.10
0.20
0.10
0.20
0.30
- 116 -
Publication Release Date: Dec. 08, 2014
Revision: A04