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W632GG8KB Datasheet, PDF (145/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM | |||
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W632GG8KB
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
SYMBOL
SPEED GRADE
PARAMETER
DDR3-1600
(-12/12I)
MIN.
MAX.
DDR3-1333
(-15/15I)
MIN.
MAX.
UNITS NOTES
Power Down Timing
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
6nS)
ï
max(3nCK,
6nS)
ï
34
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24nS)
ï
max(10nCK,
24nS)
ï
35
tCKE CKE minimum pulse width
max(3nCK,
5nS)
ï
max(3nCK,
5.625nS)
ï
tCPDED Command pass disable delay
tPD Power Down Entry to Exit Timing
1
ï
1
ï
nCK
tCKE(min) 9 * tREFI tCKE(min) 9 * tREFI
25
tACTPDEN Timing of ACT command to Power Down entry
1
ï
1
ï
nCK
27
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
1
ï
1
ï
nCK
27
tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1
ï
RL + 4 + 1
ï
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.: ï
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + WR + 1
Max.: ï
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.: ï
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 + WR + 1
Max.: ï
tREFPDEN Timing of REF command to Power Down entry
1
ï
1
ï
nCK
nCK
20
nCK
19
nCK
20
nCK
19
nCK 27, 28
tMRSPDEN Timing of MRS command to Power Down entry
tMOD(min)
ï
tMOD(min)
ï
ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4
ï
4
ï
nCK
30
ODTH8
ODT high time with Write command and burst
length 8
6
ï
6
ï
nCK
31
tAONPD
tAOFPD
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
2
8.5
2
8.5
nS
32
2
8.5
2
8.5
nS
32
tAON RTT turn-on
-225
225
-250
250
pS 17, 43
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
0.3
0.7 tCK(avg) 17, 44
tADC RTT dynamic change skew
0.3
0.7
0.3
0.7 tCK(avg) 17
Write Leveling Timing
tWLMRD
First DQS/DQS# rising edge after write leveling
mode is programmed
40
ï
40
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
25
ï
25
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
165
ï
195
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
165
ï
195
tWLO Write leveling output delay
0
7.5
0
tWLOE Write leveling output error
0
2
0
ï
nCK
5
ï
nCK
5
ï
pS
ï
pS
9
nS
2
nS
- 145 -
Publication Release Date: Dec. 08, 2014
Revision: A04
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