W632GG8KB Datasheet, PDF (17/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
8.3.1 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It
controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for
precharge Power Down, which include various vendor specific options to make DDR3 SDRAM useful
for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#,
BA0, BA1 and BA2, while controlling the states of address pins according to the Figure 5 below.
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field
0^*1
0
0
0^*1
PPD
WR
DLL TM
CL
RBT CL
BL
Mode Register 0
BA1
0
0
1
1
A8 DLL Reset
0
No
1
Yes
BA0
0
1
0
1
MRS mode
MR0
MR1
MR2
MR3
A12 DLL Control for Precharge PD
0
Slow exit (DLL off)
1
Fast exit (DLL on)
A7 Mode
0 Normal
1
Test
Write recovery for Auto precharge
A11 A10 A9 WR(cycles)
000
16^*2
001
5^*2
010
6^*2
011
7^*2
100
8^*2
101
10^*2
110
12^*2
111
14^*2
A3 Read Burst Type
0 Nibble Sequential
1
Interleave
Burst Length
A1 A0
BL
00
8 (Fixed)
0 1 BC4 or 8 (on the fly)
10
BC4 (Fixed)
11
Reserved
CAS Latency
A6 A5 A4 A2 Latency
0 0 0 0 Reserved
0 0 1 0 Reserved
0100
6
0110
7
1000
8
1010
9
1100
10
1110
11
0 0 0 1 Reserved
0011
13
0 1 0 1 Reserved
0 1 1 1 Reserved
1 0 0 1 Reserved
1 0 1 1 Reserved
1 1 0 1 Reserved
1 1 1 1 Reserved
Notes:
1. BA2, A13 and A14 are reserved for future use and must be programmed to “0” during MRS.
2. WR (write recovery for Auto precharge)min in clock cycles is calculated by dividing tWR (in nS) by tCK (in nS) and rounding
up to the next integer: WRmin[cycles] = Roundup(tWR[nS] / tCK(avg)[nS]). The WR value in the mode register must be
programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported CAS Latency, please refer to “Speed
Bins” tables for each frequency.
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 5 – MR0 Definition
8.3.1.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type
is selected via bit A3 as shown in Figure 5. The ordering of accesses within a burst is determined by
the burst length, burst type, and the starting column address as shown in Table 1. The burst length is
defined by bits A0-A1. Burst length options include fixed BC4, fixed BL8 and ‘on the fly’ which allows
BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#.
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Publication Release Date: Jul. 28, 2014
Revision: A04