W632GG8KB Datasheet, PDF (5/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
1. GENERAL DESCRIPTION
The W632GG8KB is a 2G bits DDR3 SDRAM, organized as 33,554,432 words  8 banks  8 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. The W632GG8KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I.
The -11 grade is compliant to the DDR3-1866 (13-13-13) specification. The -12 and 12I grades are
compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is guaranteed to
support -40°C ≤ TCASE ≤ 95°C). The -15 and 15I grades are compliant to the DDR3-1333 (9-9-9)
specification (the 15I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C).
The W632GG8KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
 Power Supply: VDD, VDDQ = 1.5V ± 0.075V
 Double Data Rate architecture: two data transfers per clock cycle
 Eight internal banks for concurrent operation
 8 bit prefetch architecture
 CAS Latency: 6, 7, 8, 9, 10, 11 and 13
 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
 Programmable read burst ordering: interleaved or nibble sequential
 Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
 Edge-aligned with read data and center-aligned with write data
 DLL aligns DQ and DQS transitions with clock
 Differential clock inputs (CK and CK#)
 Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
 Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
 Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
 Auto-precharge operation for read and write bursts
 Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
 Precharged Power Down and Active Power Down
 Data masks (DM) for write data
 Programmable CAS Write Latency (CWL) per operating frequency
 Write Latency WL = AL + CWL
 Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
 System level timing calibration support via write leveling and MPR read pattern
Publication Release Date: Jul. 28, 2014
Revision: A04
-5-