W632GG8KB Datasheet, PDF (157/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
Table 56 – Derating values for DDR3-1333/1600 tDS/tDH - (AC150)
DQ
Slew
rate
(V/nS)
4.0 V/nS
ΔtDS ΔtDH
3.0 V/nS
ΔtDS ΔtDH
ΔtDS, ΔtDH derating in [pS] AC/DC based^*
DQS, DQS# Differential Slew Rate
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
1.2 V/nS
ΔtDS ΔtDH
2.0
75
50
75
50
75
50
-
-
-
-
-
-
-
-
1.5
50
34
50
34
50
34
58
42
-
-
-
-
-
-
1.0
0
0
0
0
0
0
8
8
16
16
-
-
-
-
0.9
-
-
0
-4
0
-4
8
4
16
12
24
20
-
-
0.8
-
-
-
-
0
-10
8
-2
16
6
24
14
32
24
0.7
-
-
-
-
-
-
8
-8
16
0
24
8
32
18
0.6
-
-
-
-
-
-
-
-
15 -10 23
-2
31
8
0.5
-
-
-
-
-
-
-
-
-
-
14 -16 22
-6
0.4
-
-
-
-
-
-
-
-
-
-
-
-
7
-26
Note: Cell contents ‘-’ are defined as not supported.
Table 57 – Derating values for DDR3-1866 tDS/tDH - (AC135)
1.0 V/nS
ΔtDS ΔtDH
-
-
-
-
-
-
-
-
-
-
40
34
39
24
30
10
15 -10
DQ
Slew
rate
(V/nS)
8.0 V/nS
7.0 V/nS
ΔtDS, ΔtDH derating in [pS] AC/DC based^*
Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
Alternate DC100 Threshold -> VIH(DC)=VREF(DC)+100mV, VIL(DC)=VREF(DC)-100mV
DQS, DQS# Differential Slew Rate
6.0 V/nS 5.0 V/nS 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
4.0 34 25 34 25 34 25 - - - - - - - - - - - - - - - - - -
3.5 29 21 29 21 29 21 29 21 - - - - - - - - - - - - - - - -
3.0 23 17 23 17 23 17 23 17 23 17 - - - - - - - - - - - - - -
2.5 - - 14 10 14 10 14 10 14 10 14 10 - - - - - - - - - - - -
2.0 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - -
1.5 - - - - - - -23 -17 -23 -17 -23 -17 -23 -17 -15 -9 - - - - - - - -
1.0 - - - - - - - - -68 -50 -68 -50 -68 -50 -60 -42 -52 -34 - - - - - -
0.9 - - - - - - - - - - -66 -54 -66 -54 -58 -46 -50 -38 -42 -30 - - - -
0.8 - - - - - - - - - - - - -64 -60 -56 -52 -48 -44 -40 -36 -32 -26 - -
0.7 - - - - - - - - - - - - - - -53 -59 -45 -51 -37 -43 -29 -33 -21 -17
0.6 - - - - - - - - - - - - - - - - -43 -61 -35 -53 -27 -43 -19 -27
0.5 - - - - - - - - - - - - - - - - - - -39 -66 -31 -56 -23 -40
0.4 - - - - - - - - - - - - - - - - - - - - -38 -76 -30 -60
Note: Cell contents ‘-’ are defined as not supported.
Table 58 – Required time tVAC above VIH(AC) {below VIL(AC)} for valid DQ transition
DDR3-1333/1600 (AC150)
DDR3-1866 (AC135)
Slew Rate [V/nS]
tVAC [pS]
tVAC [pS]
Min.
Max.
Min.
Max.
> 2.0
105
-
93
-
2.0
105
-
93
-
1.5
80
-
70
-
1.0
30
-
25
-
0.9
13
-
Note
-
0.8
Note
-
Note
-
0.7
Note
-
-
-
0.6
Note
-
-
-
0.5
Note
-
-
-
< 0.5
Note
-
-
-
Note: Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than
VIL(AC) level.
- 157 -
Publication Release Date: Dec. 08, 2014
Revision: A04