W632GG8KB Datasheet, PDF (130/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
Table 47 – IDD5B Measurement-Loop Pattern¹
Data²
0
0
REF 0 0 0 1 0 0 0 0 0 0 0
-
1, 2
D, D 1 0 0 0 0 0 0 0 0 0 0
-
3, 4
D#, D# 1 1 1 1 0 0 0 0 0 F 0
-
5...8
Repeat cycles 1...4, but BA[2:0] = 1
9...12
Repeat cycles 1...4, but BA[2:0] = 2
1
13...16
Repeat cycles 1...4, but BA[2:0] = 3
17...20
Repeat cycles 1...4, but BA[2:0] = 4
21...24
Repeat cycles 1...4, but BA[2:0] = 5
25...28
Repeat cycles 1...4, but BA[2:0] = 6
29...32
Repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC - 1 Repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
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Publication Release Date: Dec. 08, 2014
Revision: A04