W632GG8KB Datasheet, PDF (108/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
10.7.1.1 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is
defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 28
and Figure 94.
Table 28 – Single-ended Output Slew Rate Definition
Description
Measured
from
to
Defined by
Single-ended output slew rate for rising edge VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)] / ΔTRse
Single-ended output slew rate for falling edge VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)] / ΔTFse
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
ΔTRse
VOH(AC)
VTT
VOL(AC)
ΔTFse
Figure 94 –Single-ended Output Slew Rate Definition
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Publication Release Date: Dec. 08, 2014
Revision: A04