W632GG8KB Datasheet, PDF (40/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
T0
CK#
CK
Ta
Tb0
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Command
PREA
MRS
READ^*1
READ^*1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
tRP
tMOD
tCCD
tMPRR
BA
3
VALID
VALID
3
A[1:0]
0
0^*2
0^*2
VALID
A[2]
1
0^*3
1^*4
0
A[9:3]
00
VALID
VALID
00
A10/AP
1
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12/BC#
0
VALID^*1
VALID^*1
0
DQS, DQS#
DQ
RL
RL
NOTES:
1. RD with BC4 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
Figure 19 – MPR Readout pre-defined pattern, BC4, lower nibble then upper nibble
Tc9
T10
Td
NOP
NOP
tMOD
VALID
TIME BREAK
DON'T CARE
- 40 -
Publication Release Date: Jul. 28, 2014
Revision: A04