W632GG8KB Datasheet, PDF (104/159 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB
Table 21 – Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#
DDR3-1333/1600
DDR3-1866
Slew Rate
[V/nS]
tDVAC [pS]
@ VIH/LDIFF(AC) =
350mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
300mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
300mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
(CK - CK#) only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
> 4.0
75
-
175
-
134
-
139
-
4.0
57
-
170
-
134
-
139
-
3.0
50
-
167
-
112
-
118
-
2.0
38
-
119
-
67
-
77
-
1.8
34
-
102
-
52
-
63
-
1.6
29
-
81
-
33
-
45
-
1.4
22
-
54
-
9
-
23
-
1.2
Note
-
19
-
Note
-
Note
-
1.0
< 1.0
Note
-
Note
-
Note
-
Note
-
Note
-
Note
Note
-
Note
-
Note:
Rising input differential signal shall become equal to or greater than VIHDIFF(AC) level and Falling input differential signal shall
become equal to or less than VILDIFF(AC) level.
10.6.4 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, CK#, DQS#) has also to comply with
certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the AC-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
DQS, DQS # have to reach VSEHmin / VSELmax (approximately the AC-levels (VIH.DQ(AC) / VIL.DQ(AC) )
for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these AC-levels apply also for the
single-ended signals CK and CK#.
Table 22 – Single-ended levels for CK, DQS, CK#, DQS#
PARAMETER
SYM.
DDR3-1333, DDR3-1600 & DDR3-1866
MIN.
MAX.
UNIT NOTES
Single-ended high level for strobes
Single-ended high level for CK, CK#
VSEH
(VDD/2) + 0.175
(VDD/2) + 0.175
Note 3
Note 3
V
1, 2
V
1, 2
Single-ended low level for strobes
Single-ended low level for CK, CK#
VSEL
Note 3
Note 3
(VDD/2) - 0.175
(VDD/2) - 0.175
V
1, 2
V
1, 2
Notes:
1. For CK, CK# use VIH.CA(AC) / VIL..CA(AC) of ADD/CMD; for strobes (DQS, DQS#) use VIH.DQ(AC) / VIL.DQ(AC) of DQs.
2. VIH.DQ(AC) / VIL.DQ(AC) for DQs is based on VREFDQ; VIH.CA(AC) / VIL.CA(AC) for ADD/CMD is based on VREFCA; if a
reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS# need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to
section 10.12 “Overshoot and Undershoot Specifications” on page 121.
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Publication Release Date: Dec. 08, 2014
Revision: A04