W925E240 Datasheet, PDF (65/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
A/B Wires
RNG
CIDE
CIDF
TE DC load
TE AC load
FSKE
FCD
FDR
FCLK
FDATA
Line Reversal
Ring Burst
A
B
Ch. Seizure Mark Message
C
D
E
F
First Ring Cycle
...
250 - 400 ms
Note 2
Note 1
...
50 - 150 ms
Note 4
Note 3
...
...101010...
...
A = 200 - 450mS
B >= 500mS
C = 80 - 262mS
D = 45 - 262mS
E <= 2.5sec (500ms typical)
Data
F >= 200mS
Figure 7-6 Input and Output Timing of CCA Caller Display Service Data Transmission
Notes:
1. The CPE designer may choose to set FSKE always high while the CPE is on-hook and the FSK signal is expected.
2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250 - 400 mS after the end of the ring
burst.
3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50 - 150 ms after the end of the FSK
signal.
4. The CID may not be enable up at the first ring cycle after the FSK data had been processed.
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Publication Release Date: July 12, 2005
Revision A10