W925E240 Datasheet, PDF (45/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
RWT:
WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to restart
it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically
clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by the user within
512 clocks of the time-out. If this is not done then a Watchdog timer reset will occur.
CLOCK CONTROL
WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the time-
out interval for the watchdog timer. The reset time is longer 512 clocks time than the
interrupt time-out value.
The default Watchdog time-out is 2¹² clocks, which is the shortest time-out period. The EWT, WDIF
and RWT bits are protected by the Timed Access procedure. This prevents software from accidentally
enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant
code can enable or disable the watchdog timer.
6.9 Serial Port 1
The P4.0 and P4.1 can be used as an 8-bit serial input/output port1. P4.0 is the serial port 1 clock I/O
pin and P4.1 is the serial port 1 data I/O pin. The serial port 1 is controlled by SCON1 register which is
described as below.
SF1: Serial port 1 interrupt flag. When an 8-bits data are transit completely, SF1 is set by hardware.
SF1 is cleared when serial interrupt1 routine is executed or cleared by software.
REN1: Set REN1 from 0 to 1 to start the serial port1 to receive 8-bit serial data.
SFQ: SFQ = 0 Serial clock output frequency is equal to f_OSC /2
SFQ = 1 Serial clock output frequency is equal to f_OSC / 256
SEDG: SEDG = 0 Serial data latched at falling edge of clock, SCLK=Low initially.
SEDG = 1 Serial data latched at rising edge of clock, SCLK=High initially.
CLKIO: CLKIO = 0 P4.0(SCLK) work as output mode
CLKIO = 1 P4.0(SCLK) work as input mode
SIO: SIO = 0 P4.0 & P4.1 work as normal I/O pin
SIO = 1 P4.0 & P4.1 work as Serial port1 function
Any instruction causes a write to SBUF1 will start the transmission of serial port 1. As the REN1 is
from 0 to 1, the serial port 1 begins to receive a byte into SBUF1 in the frequency of the serial clock.
REN1 could be cleared by software after receive function begins. The LSB is transmitted/ received
first. The I/O mode of serial clock pin is controlled by CLKIO. User has to take care the initial state of
the serial port pins.
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Publication Release Date: July 12, 2005
Revision A10