W925E240 Datasheet, PDF (44/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a
known state. The RWT bit is used to restart the watchdog timer. This bit is self-clearing, i.e. after
writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock
cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6).
When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the
time-out has occurred, the watchdog timer waits for an additional 512 clock cycles. The software must
issue a RWT to reset the watchdog before the 512 clocks have elapsed. If the Watchdog Reset EWT
(WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system reset due to
Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer reset flag
WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the cause of the
reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a
very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an
interrupt will occur if the global interrupt enable EA is set.
Table 6 Time-out values for the Watchdog timer
WD1
0
0
1
1
WD0
0
1
0
1
WATCHDOG
INTERVAL
2¹²
2¹⁵
2¹⁸
2²¹
NUMBER OF
CLOCKS
4096
32786
262144
2097152
FOSC =
3.579545 MHZ
1.14 mS
9.15 mS
73.23 mS
585.87 mS
FOSC =
32768 HZ
0.125 S
1S
8S
64 S
RESET OF
CLOCKS
4608
33280
262656
2097664
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into
a known state.
The control bits that support the Watchdog timer are discussed below.
WATCHDOG CONTROL
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the
global interrupt enable is set and other interrupt requirements are met). Software or any reset
can clear this bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
This bit is useful for determined the cause of a reset. Software must read it, and clear it
manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by
the watchdog timer.
EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog
timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will
leave the timer running
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