W925E240 Datasheet, PDF (40/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
Table 4 Interrupt table.
INTERRUPT
External
interrupt 0
Timer0
overflow
FLAG
NAME
IE0
TF0
FLAG
LOCATION
TCON.1
TCON.5
EN BIT
EX0
ET0
EN BIT
LOCATION
PRIORITY
FLAG
CLEARED BY
INTERRUPT
VECTOR
IE.0
1
(higest)
hardware +
software
03h
IE.1
2
hardware +
software
0Bh
External
interrupt 1
IE1 TCON.3 EX1
IE.2
3
hardware +
software
13h
Timer1
overflow
Serial port
External
interrupt 2
TF1 TCON.7
ET1
SF1 SCON1.7 ES1
IE2
EXIF.0
EX2
IE.3
IE.6
EIE.0
4
hardware +
software
1Bh
5
hardware +
software
3Bh
6
hardware +
software
43h
External
interrupt 3
CID
IE3
CIDF
EXIF.1
EXIF.2
EX3
ECID
EIE.1
EIE.2
7
hardware +
software
4Bh
8
software
53h
Divider
overflow
DIVF EXIF.3
EDIV
EIE.3
9
hardware +
software
5Bh
Compare
difference
COMPF EXIF.4
ECOMP
EIE.4
10
hardware +
software
63h
Watchdog
timer
WDIF WDCON.3 EWDI
EIE.5
11
(lowest)
software
6Bh
Ps: The flags marked as the italic font are not bit-addressable.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI.
If any of these conditions is not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts being sampled in the same machine cycle. If an
interrupt flag is active in one cycle but not responded to, and is not active when the above conditions
are met, the denied interrupt will not be serviced. This means that active interrupts are not
remembered. Note that every polling cycle is new.
Execution continues from the vectored address until an RETI instruction is executed. On execution of
the RETI instruction, the processor pops out the top content of Stack to the PC. The processor is not
notified anything if the content of stack was changed. Note that a RET instruction would perform
exactly the same process as a RETI instruction, but it would not inform the Interrupt Controller that the
interrupt service routine is completed, and would leave the controller still thinking that the service
routine is underway.
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