W925E240 Datasheet, PDF (50/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
When FTE enable will set the FDS to high to enable the internal latch clock in 1200Hz. When FDS is
in high state, FSKTB bit0 will be sent out by FSK modulator at the rising edge of latch clock. FDS
could be cleared by software to inform no more data will be sent out after the last bit is sent
completely. If the FDS is cleared then FTE will become low at next rising latch clock to disable FSK
modulator and clear FDS by hardware automatically.
When FTE is set, FSK modulation flag (FSF) will be set at every rising edge of latch clock to produce
an interrupt shared with CID interrupt routine. If a CID interrupt occurs, user can check FSF to know if
this interrupt is caused by FSK modulator. The only way to stop FSK signal immediately is to disable
FTE by software.
6.13 I/O Ports
There are five 8-bits ports named from P0 to P4 in W925E/C240. All ports can be configured as input
or output mode. Except P0, every port has pull high resistor enable/disable by PxH register. After reset
the initial state of each port is in input mode and the value of the registers from P0 to P3 are FFh. The
I/O port is described as below:
P0: I/O mode is controlled by P0IO. Only P0 output as open drain mode and without pull high
resistor.
P1: I/O mode is controlled by P1IO. Pull high is controlled by P1H. P1.0~P1.3 work as INT2,
P1.4~P1.7 work as INT3. Falling edge on P1 pins to produce INT2 and INT3 flag. P1 is
configured as INT2/INT3 by P1EF register.
P2: I/O mode is controlled by P2IO. Pull high is controlled by P2H.
P3: I/O mode is controlled by P3IO. Pull high is controlled by P3H.
P3.5
T1
Timer/counter 1 external count input
P3.4
T0
Timer/counter 0 external count input
P3.3
INT1
External interrupt 1
P3.2
INT0
External interrupt 0
P4: I/O mode is controlled by P4IO. Pull high is controlled by P4H.
Special function of P4 is described below.
P4.7-5 I/O
Normal I/O
P4.4
VPOS
Positive input of the comparator
P4.2
VNEG
Negative input of the comparator
P4.1
SDATA Serial port output
P4.0
SCLK
Serial port input
6.14 Divider
A built-in 13/14-bit binary up counter designed to generate periodic interrupt. The clock source is from
sub-oscillator. When the frequency of sub-crystal is 32768Hz, it provides the divider interrupt in the
period of 0.25/0.5 second. Bit DIVS controls the degree of divider. When DIVA is high to enable the
divided counter, when DIVA is low to reset divider and stop counting. As the divider overflows, the
divider interrupt flag DIVF is set. DIVF is clear by software or serving divider interrupt routine.
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