W925E240 Datasheet, PDF (29/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
DIVIDER CONTROL
(initial = 01H)
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DIVA
Mnemonic: DIVC
Address: C8h
DIVA: Divider available control bit. This bit is set or cleared by software to enable/disable divider. DIVA
= 1 to enable the divider. DIVA = 0 to disable the divider. DIVA is reset after reset.
PROGRAM STATUS WORD
(initial = 00H)
Bit:
7
6
5
4
3
2
1
0
CY
AC
F0
RS1 RS0
OV
F1
P
Mnemonic: PSW
Address: D0h
CY: Carry flag. Set for an arithmetic operation, which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
AC: Auxiliary carry. Set when the previous operation resulted in a carry from the high order nibble.
F0: User flag 0. General-purpose flag that can be set or cleared by the user.
RS.1-0: Register bank select bits:
RS1 RS0 Register bank Address
0
0
0
00-07h
0
1
1
08-0Fh
1
0
2
10-17h
1
1
3
18-1Fh
OV: Overflow flag. Set when a carry was generated from the seventh bit but not from the 8th bit as a
result of the previous operation, or vice-versa.
F1: User Flag 1. General-purpose flag that can be set or cleared by the user by software.
P: Parity flag. Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
WATCHDOG CONTROL
(initial: note)
Bit:
7
-
6
5
4
3
2
1
0
POR
-
WFS WDIF WTRF EWT RWT
Mnemonic: WDCON
Address: D8h
POR: Power-on reset flag. Hardware will set this flag when system is powered on and this flag is
cleared only by software.
WFS: Watchdog Timer Frequency Select. Set to select F_S as WDT clock input. Clear to select F_OSC as
WDT clock input.
WDIF: Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the watchdog
timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the global
interrupt enable is set and other interrupt requirements are met). Software or any reset can
clear this bit.
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Publication Release Date: July 12, 2005
Revision A10