W925E240 Datasheet, PDF (33/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
6.4 Instruction
The W925E/C240 executes all the instructions of the standard 8032 family. However, timing of these
instructions is different. In the W925E/C240, each machine cycle consists of 4 clock periods, while in
the standard 8032 it consists of 12 clock periods. Also, in the W925E/C240 there is only one fetch per
machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine
cycle, which works out to 6 clocks per fetch.
Table 2 Instructions that affect Flag settings
INSTRUCTION CARRY
OVERFLOW
AUXILIARY
CARRY
INSTRUCTION
INC, DEC
-
-
-
SETB C
ADD
X
X
X
CLR C
ADDC
X
X
X
CPL C
SUBB
X
X
X
ANL C, bit
MUL
0
X
ANL C, bit
DIV
0
X
ORL C, bit
DA A
X
ORL C, bit
RRC A
X
MOV C, bit
RLC A
X
CJNE
CARRY
1
0
X
X
X
X
X
X
X
OVERFLOW
AUXILIARY
CARRY
A "X" indicates that the modification is as per the result of instruction.
A "-" indicates that the flag is not effected by the instruction.
INSTRUCTION
NOP
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
Table 3 Instruction Timing for W925E/C240
HEX
OP-CODE
00
28
29
2A
2B
2C
2D
2E
2F
26
27
25
24
38
39
BYTES
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
MACHINE
CYCLES
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
INSTRUCTION
ANL A, R0
ANL A, R1
ANL A, R2
ANL A, R3
ANL A, R4
ANL A, R5
ANL A, R6
ANL A, R7
ANL A, @R0
ANL A, @R1
ANL A, direct
ANL A, #data
ANL direct, A
ANL direct, #data
ANL C, bit
HEX
OP-CODE
BYTES
58
1
59
1
5A
1
5B
1
5C
1
5D
1
5E
1
5F
1
56
1
57
1
55
2
54
2
52
2
53
3
82
2
MACHINE
CYCLES
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
- 33 -
Publication Release Date: July 12, 2005
Revision A10