W925E240 Datasheet, PDF (18/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
EXTERNAL INTERRUPT FLAG
(initial = 00H)
Bit:
7
6
5
4
3
2
1
0
-
-
- COMPF DIVF CIDF IE3
IE2
Mnemonic: EXIF
Address: 91h
COMPF: Comparator flag. Set by hardware when RESC bit is from low to high.
DIVF: Divider overflow flag.
CIDF: CID interrupt flag. Set by hardware when at least one of CID flags is set.
IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3.
IE2: External Interrupt 2 flag. Set by hardware when a falling edge is detected on INT2.
ROM PAGE POINTER
(initial = 00H)
Bit:
7
6
5
4
3
2
1
0
-
-
LT1 LT0
-
-
-
PG
Mnemonic: RPAGE
Address: 92h
LT1 and LT0 determine the ROM page of the instruction MOVC reading the content from ROM.
ROM PAGE Rom address
(LT1, LT0) = (0, 0)
Page 0
00000H-0FFFFH
(LT1, LT0) = (0, 1)
Page 1
10000H-1FFFFH
(LT1, LT0) = (1, 0)
Page 2
20000H-2FFFFH
(LT1, LT0) = (1, 1)
Page 3
30000H-3FFFFH
PG = 0 indicates the executing program is in page 0, from 00000H-0FFFFH
PG = 1 indicates the executing program is in page 1, from 10000H-1FFFFH
P1 PINS STATUS
(initial = 00H)
Bit:
7
6
5
4
3
2
1
0
P1.7SR P1.6SR P1.5SR P1.4SR P1.3SR P1.2SR P1.1SR P1.0SR
Mnemonic: P1SR
Address: 93h
P1SR: Set when a falling edge is detected on the corresponding P1 pin, clear by software.
P0 I/O PORT CONTROL
(initial = FFH)
Bit:
7
6
5
4
3
2
1
0
P0.7IO P0.6IO P0.5IO P0.4IO P0.3IO P0.2IO P0.1IO P0.0IO
Mnemonic: P0IO
P0IO: P0 pins I/O control.
1: input mode
0: output mode
Address: 94h
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