W925E240 Datasheet, PDF (22/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
PORT 3
(initial = FFH,input mode)
Bit:
7
6
5
4
3
2
1
0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
Mnemonic: P3
Address: B0h
P3.7-0: P3 can be selected as input or output mode by the P3IO register, at initial reset, P3IO is set to
0FFH, P3 is used as input mode. When P3IO is set to 00h, the P3 is used as CMOS output
mode. Special function of P3 is described below.
P3.5
T1
Timer/Counter 1 external count input
P3.4
T0
Timer/Counter 0 external count input
P3.3
INT1
External interrupt 1
P3.2
INT0
External interrupt 0
CID REGISTER
(initial = 00H,read only)
Bit:
7
6
5
4
3
2
1
0
-
FCLK FDATA FCD DTMFD FDR ALGO RNG
Mnemonic: CIDR
Address: B1h
This SFR indicates the CID signal immediately. Register data is set or cleared by hardware only.
FCLK: FSK serial clock with the baud rate of 1200Hz.
FDATA: FSK serial bit data.
FCD: Set when FSK carrier is detected. Cleared when FSK carrier is disappeared.
DTMFD: Set when DTMF decoded data is ready. Cleared when DTMF signal ends.
FDR: Set when FSK 8 bits data is ready. Cleared before next FSK start bit comes
ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone
alert signal has been detected. Cleared when the guard time qualified dual tone alert signal is
absent.
RNG: Ring detection bit. High to indicate the detection of line reversal and/or ringing.
CID FLAG GENERATOR
(initial = 00H)
Bit:
7
6
5
4
3
2
1
0
-
-
-
FSF DTMFDF FDRF ALGOF RNGF
Mnemonic: CIDFG
Address: B2h
FSF: Set when FSK Latch clock low to high. Cleared by software
DTMFDF: Set when DTMFD low to high. Cleared by software
FDRF: Set when FDR low to high. Cleared by software.
ALGOF: Set when ALGO low to high. Cleared by software.
RNGF: Set when RNG low to high. Cleared by software.
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