W925E240 Datasheet, PDF (58/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
CID Input Gain Control
The CID input gain and input hysteresis are controllable by internal CID gain control registers. CIDGD
and CIDGA registers determine the 6 internal CID gain control registers. CID gain control data register
(CIDGD) presents the data bus. The lower 3 bits of CID gain control address register (CIDGA) present
the address. The rising edge of CIDGA.4 will latch the CIDGD in the corresponding internal CID gain
control register. The 6 internal CID gain control registers are addressed as following table. Setting the
6 registers as the suggestion value guarantees the CID spec.
ADDRESS
(CIDGA.2-0)
INTERNAL CID GAIN CONTROL REGISTER
SUGGESTION
VALUE
000
DTMFR1: DTMF register1
001
DTMFR2: DTMF register2
0000 0001B
011X 0001B^Ê
002
PGAF: Programmable gain control alert tone and FSK
99H
003
PGAD: Programmable gain control DTMF
A7H
004
PHAD: Programmable hysteresis alert tone and DTMF
35H
005
PHFL: Programmable hysteresis FSK and low pass filter 33H
Ê _{X = 0 DTMF receiver works a DTMF decoder, X=1 DTMF receiver works as a tone detector.}
The signals to set internal CID gain control registers is shown in Figure 6-22
CIDGA
CIDGA<2:0>
CIDGD
CIDGD
CIDGA.3
Rising latch
Figure 6-22 Internal CID Gain Control Register Setting Waveform
DTMFR1
DTMFR1[7:4] are reserved bits and must be 0000b.
BIT3~BIT0
ACCEPTABLE ERROR PERCENTAGE TO SAMPLE 4 PERIOD OF ROW FREQ.
0000
0.6% (default)
0001
2.5%
001X
3.5%
01XX
Reserved
1XXX
Reserved
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