W925E240 Datasheet, PDF (57/73 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925E/C240
FSK Decoder
The FSK carrier detector provides an indication of the present of a signal within the FSK frequency
band. If the output amplitude of the FSK band-pass filter is sufficient to be detected continuously for 8
mS, the FSK carrier detected bit FCD will go high and it will be released if the FSK band-pass filter
output amplitude is not able to be detected for greater than 8 mS. The 8 mS is the hysteresis of the
FSK carrier detector. Figure 6-20 shows the timing of FSK carrier detection.
Tip/Ring
FSKE
FCD
t _FSKE ^{Analog FSK Signal}
Note
t _CA
t _CP
Analog FSK Signal
t _CP
t _CA
Figure 6-20 FSK Detection Enable and FSK Carrier Present and Absent Timing
The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying
(FSK) with 1200-baud rate. When the decoder receives the FSK serial data, the serial data will be
demodulated into bit FDATA with 1200-baud rate in the mean time the synchronous clock signal is
output to the bit FCLK. As the decoder receives one byte, the internal serial-to-parallel circuit sets the
bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge of bit FDR will
set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User can get the FSK
data by reading register FSKDR or sampling the bit FDATA. The timing of FSK demodulation is shown
in Figure 6-21.
Tip/Ring
start
1st byte data
stop
start
2nd byte data
stop
start
1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0
t_IDD
FDATA
start
1st byte data
b0 b1 b2 b3 b4 b5 b6 b7
stop
start
2nd byte data
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
1/f_DCLK0
FCLK
t_CRD
t _RH
FDR
FDRF
FSKDR
* Mark bit or redundant stop bit(s), will be omitted.
+ Clear by software.
+
1st byte data
2nd byte data
Figure 6-21 Serial Data Interface Timing of FSK Demodulation
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Publication Release Date: July 12, 2005
Revision A10