W3H32M72E-XSBX Datasheet, PDF (6/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
DESCRIPTION
The 2Gb DDR2 SDRAM is a high-speed CMOS, dynamic
random-access memory containing 2,147,483,648 bits.
Each of the five ships in the MCP are internally configured
as 4-bank DRAM. The block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
The 2Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O balls. A single read or write
access for the 2Gb DDR2 SDRAM effectively consists of
a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and four corresponding n-bit-wide,
one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during
WRITEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRITEs. There are strobes,
one for the lower byte (LDQS, LDQS#) and one for the
upper byte (UDQS, UDQS#).
The 2Gb DDR2 SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another write.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the
burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving
power-down mode.
All inputs are compatible with the JEDEC standard for
SSTL_18. All full drive-strength outputs are SSTL_18-
compatible.
GENERAL NOTES
• The functionality and the timing specifications
discussed in this data sheet are for the DLL-
enabled mode of operation.
• Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0–DQ7), DM refers to
LDM and DQS refers to LDQS. For the upper byte
(DQ8–DQ15), DM refers to UDM and DQS refers to
UDQS. Note that the there is no upper byte for U4
and therefore no UDM4.
• Complete functionality is described throughout
the document and any page or diagram may have
been simplified to convey a topic and may not be
inclusive of all requirements.
• Any specific requirement takes precedence over a
general statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
The following sequence is required for power up and
initialization and is shown in Figure 4 on page 8.
1. Applying power; if CKE is maintained below 0.2 x
VCCQ, outputs remain disabled. To guarantee RTT
(ODT resistance) is off, VREF must be valid and a
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
6
White Electronic Designs Corporation • [phone] • www.wedc.com