W3H32M72E-XSBX Datasheet, PDF (12/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of
the first bit of output data. The CL can be set to 3, 4, 5,
or 6 clocks, depending on the speed grade option being
used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AL). This feature allows the READ
command to be issued prior to ^tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
Examples of CL = 3 and CL = 4 are shown in Figure 6;
both assume AL = 0. If a READ command is registered
at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n+m (this
assumes AL = 0).
FIGURE 6 – CAS LATENCY (CL)
T0
T1
T2
T3
T4
T5
T6
CK#
CK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3 (AL = 0)
CK#
CK
COMMAND
DQS, DQS#
DQ
T0
READ
T1
T2
T3
NOP
NOP
NOP
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal ^t AC, ^t DQSCK, and ^t DQSQ
T4
T5
T6
NOP
NOP
NOP
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
TRANSITIONING DATA
DON’T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
12
White Electronic Designs Corporation • [phone] • www.wedc.com