W3H32M72E-XSBX Datasheet, PDF (15/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 define the value
of AL, as shown in Figure 7. Bits E3–E5 allow the user
to program the DDR2 SDRAM with an inverse AL of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
WRITE command to be issued prior to ^tRCD (MIN) with
the requirement that AL ≤ ^tRCD (MIN). A typical application
using this feature would set AL = ^tRCD (MIN) - 1x ^tCK. The
READ or WRITE command is held for the time of the AL
before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL+CL.
Write latency (WL) is equal to RL minus one clock; WL =
AL + CL - 1 x ^tCK.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EMR2 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹ 0¹
Extended Mo de
Register (Ex)
M15 M14 Mode Register Definition
00
Mo de Register (MR)
0 1 Extended Mo de Register (EMR)
1 0 Extended Mo de Register (EMR2)
1 1 Extended Mo de Register (EMR3)
E7 High Temperature Self Refresh rate enable
0 Commer cial-Temperature default
1 ^{Industrial-Temperature option;}
use if T_Cexceeds 85°C
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
15
White Electronic Designs Corporation • [phone] • www.wedc.com