W3H32M72E-XSBX Datasheet, PDF (26/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
AC TIMING PARAMETERS
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
533Mbs CL4
400Mbs CL3
Symbol
Unit
Min Max Min Max
Clock cycle time
CK high-level width
CK low-level width
Half clock period
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
DQ-DQS hold, DQS to first DQ to go nonvalid, per access
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
O DQS-DQ skew, DOS to last DQ valid, per group, per access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching transition
CL=4
CL=3
tCK(4) 3,750 8,000 5,000 8,000 ps
tCK(3) 5,000 8,000 5,000 8,000 ps
tCH
0.48 0.52 0.48 0.59
tCK
tCL
0.48 0.52 0.48 0.59
tCK
tHP
MIN (tCH,
tCL)
MIN (tCH,
tCL)
ps
tAC
-500 +500 -600 +600
ps
tHZ
tAC(MAX)
tAC(MAX)
ps
tLZ
tAC(MN) tAC(MAX) tAC(MN) tAC(MAX)
ps
tDS
100
150
tQH
225
275
tDIPW
0.35
0.35
tCK
tQHS
400
450
ps
tHQ
tHP - tQHS
tHP - tQHS
ps
tDVW tQH - tDQSQ
tQH - tDQSQ
ns
tDQSH
0.35
0.35
tCK
tDQSL
0.35
0.35
tCK
tDQSCK -450 +450 -500 +500
Ps
tDSS
0.2
0.2
tCK
tDSH
0.2
0.2
tCK
tDQSQ
300
350
ps
tRPRE
0.9
1.1
0.9
1.1
tCK
tRPST
0.4
0.6
0.4
0.6
tCK
tWPRES
0
0
ps
tWPRE
0.25
0.25
tCK
tWPST
0.4
0.6
0.4
0.6
tCK
tDQSS WL-TDQSS WL+TDQSS WL-TDQSS WL+TDQSS tCK
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
26
White Electronic Designs Corporation • [phone] • www.wedc.com